dhr. M.E. (Merijn) Verstraaten MSc


  • Faculteit der Natuurwetenschappen, Wiskunde en Informatica
    Informatics Institute
  • Bezoekadres
    Science Park A
    Science Park 904  
  • Postadres:
    Postbus  94323
    1090 GH  Amsterdam
  • M.E.Verstraaten@uva.nl

2017

  • Verstraaten, M., Varbanescu, A. L., & de Laat, C. (2017). Synthetic graph generation for systematic exploration of graph structural properties. In F. Desprez, & P-F. Dutot (Eds.), Euro-Par 2016: Parallel Processing Workshops: Euro-Par 2016 International Workshops, Grenoble, France, August 24-26, 2016 : revised selected papers (pp. 557-570). (Lecture Notes in Computer Science; Vol. 10104). Cham: Springer. DOI: 10.1007/978-3-319-58943-5_45  [details] 

2015

  • Verstraaten, M., Varbanescu, A. L., & de Laat, C. (2015). Quantifying the performance impact of graph structure on neighbour iteration strategies for PageRank. In S. Hunold, A. Costan, D. Giménez, A. Iosup, L. Ricci, M. E. Gómez Requena, V. Scarano, A. L. Varbanescu, S. L. Scott, S. Lankes, J. Weidendorfer, ... M. Alexander (Eds.), Euro-Par 2015: Parallel Processing Workshops: Euro-Par 2015 International Workshops, Vienna, Austria, August 24-25, 2015 : revised selected papers (pp. 528-540). (Lecture Notes in Computer Science; Vol. 9523). Cham: Springer. DOI: 10.1007/978-3-319-27308-2_43  [details] 

2013

  • Verstraaten, M., Kok, S., Poss, R., & Grelck, C. (2013). Task Migration for S-Net/LPEL. In C. Grelck, K. Hammond, & S. B. Scholz (Eds.), FD-COMA 2013: 2nd HiPEAC Workshop on Feedback-Directed Compiler Optimization for Multi-Core Architectures: 8th International Conference on High-Performance and Embedded Architectures and Compilers: HIPEAC 2013: Berlin, Germany, January 21-23, 2013 (pp. [30-36]). [S.l.]: HIPEAC. [details] 
  • MacKenzie, K., Hölzenspies, P. K. F., Hammond, K., Kirner, R., Nguyen, V. T. N., te Boekhorst, R., ... Verstraaten, M. (2013). Statistical Performance Analysis of an Ant-Colony Optimisation Application in S-Net. In C. Grelck, K. Hammond, & S. B. Scholz (Eds.), FD-COMA 2013: 2nd HiPEAC Workshop on Feedback-Directed Compiler Optimization for Multi-Core Architectures: 8th International Conference on High-Performance and Embedded Architectures and Compilers: HIPEAC 2013: Berlin, Germany, January 21-23, 2013 (pp. [10-17]). [S.l.]: HIPEAC. [details] 

2011

  • Verstraaten, M., Grelck, C., van Tol, M. W., Bakker, R., & Jesshope, C. R. (2011). On mapping distributed S-Net to the 48-core Intel SCC processor. In D. Göhringer, M. Hübner, & J. Becker (Eds.), 3rd Many-core Applications Research Community (MARC) Symposium (pp. 41-46). Karlsruhe, Germany: KIT Scientific Publishing. [details] 
  • van Tol, M. W., Bakker, R., Verstraaten, M., Grelck, C., & Jesshope, C. R. (2011). Efficient memory copy operations on the 48-core Intel SCC processor. In D. Göhringer, M. Hübner, & J. Becker (Eds.), 3rd Many-core Applications Research Community (MARC) Symposium (pp. 13-18). Karlsruhe, Germany: KIT Scientific Publishing. [details] 

2017

  • Verstraaten, M. (2017). Speeding Up GPU Graph Processing Using Structural Graph Properties. Poster session presented at SuperComputing, Denver, United States.
  • Verstraaten, M., Varbanescu, A. L., & de Laat, C. (2017). Using Graph Properties to Speed-up GPU-based Graph Traversal: A Model-driven Approach. arXiv preprint arXiv:1708.01159.

2013

  • Poss, R., Verstraaten, M., Penczek, F., Grelck, C., Kirner, R., & Shafarenko, A. (2013). S+Net: extending functional coordination with extra-functional semantics. Ithaca, NY: arXiv.org. [details] 
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