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The Dynamically-scheduled Reduced Instruction Set Computer (DRISC) architecture, advanced on the eve of multi-core processors, has been used to explore how Instruction-Level Parallelism (ILP) can be traded off against how multithreading could be provisioned with simpler circuits to break the roof imposed by hardware complexity and power dissipation. Qiang Yang builds on the current research into DRISC by investigating system performance and by broadening the application of this processor design.

Event details of Exploring DRISC architecture
Date 8 April 2014
Time 14:00 -15:00
Location Agnietenkapel

Q. Yang, On the Exploration of the DRISC Architecture.

Supervisor

Prof. C.R. Jesshope

Agnietenkapel

Oudezijds Voorburgwal 229 - 231
1012 EZ Amsterdam

Entrance

This event is open to the public.